FIG. 1 shows a portion of a multi-processor computer system 100. As observed in FIG. 1, the system includes N processors 101_1 to 101_N. An operating system (OS) 102 “runs on” the processors 101_1 to 101_N. Each of the processors includes respective translation lookaside buffer (TLB) information 103_1 to 103_N. Typically, the TLB information of each processor includes both a data TLB and an instruction TLB. As is known in the art, a TLB is a table of translations between, typically, a “virtual” memory page address called out by the OS 102 or its application software, and, the actual “physical” memory page where the called out instruction or data is actually located in system memory 104. Through manipulation of TLBs, the OS 102 is able to interweave the support of multiple applications that execute out of a common address space.
As the power consumption of computing systems has become a matter of concern, most present day systems include sophisticated power management functions. FIG. 1 shows power management software 105 integrated into the OS 102. A common framework is to define both “performance” states and “power” states for each of the processors 101_1 to 101_N. A thread executing on a processor can request that processor to enter into a specific performance state or sleep state. A processor's performance is its ability to do work over a set time period. The higher a processor's performance the more work it can do over the set time period. A processor's performance can be adjusted during runtime by changing its internal clock speeds and voltage levels. As such, a processor's power consumption increases as its performance increases.
A processor's different performance states correspond to different clock settings and internal voltage settings so as to effect a different performance vs. power consumption tradeoff. According to the Advanced Configuration and Power Interface (ACPI) standard the different performance states are labeled with different “P numbers”: P0, P1, P2 . . . P_R, where, P0 represents the highest performance and power consumption state and P_R represents the lowest level of power consumption that a processor is able to perform work at. The term “R” in “P_R” represents the fact that different processors may be configured to have different numbers of performance states.
In contrast to performance states, power states are largely directed to defining different “sleep modes” of a processor. According to the ACPI standard, the C0 state is the only power state at which the processor can do work. As such, for the processor to enter any of the performance states (P0 through P_R), the processor must be in the C0 power state. When no work is to be done and the processor is to be put to sleep, the processor can be put into any of a number of different power states C1, C2 . . . C_S where each power state represents a different level of sleep and, correspondingly, a different amount of time needed to transition back to the operable C0 power state. Here, a different level of sleep means different power savings while the processor is sleeping.
A deeper level of sleep therefore corresponds to slower internal clock frequencies and/or lower internal supply voltages and/or more blocks of logic that receive a slower clock frequency and/or a lower supply voltage. Increasing C number corresponds to a deeper level of sleep. Therefore, for instance, a processor in the C2 power state might have lower internal supply voltages and more blocks of logic that are turned off than a processor in the C1 state. Because deeper power states corresponds to greater frequency and/or voltage swings and/or greater numbers of logic blocks that need to be turned on to return to the C0 state, deeper power states also take longer amounts of time to return to the C0 state.